1. Field
Embodiments of the invention relate to a method of creating an alignment mark on a substrate and a substrate formed by the method.
2. Background
In integrated circuit (IC) production, lithography is used to produce multiple stacked and overlapping circuit patterns. The production of such overlapping circuit patterns includes exposing a layer of photo-resist on a wafer. By exposing a first layer of photo-resist to a first pattern followed by some additional process steps, a first pattern is created on the wafer. Likewise, a second pattern is created on the wafer after some intermediate process steps including applying a second layer of photo-resist. The second pattern should very accurately overlap the first pattern, because at specific positions the first and the second pattern will be electrically connected. These connections are provided by intermediate vias which are formed by exposing a third layer of photo-resist on the wafer (before applying and exposing the second layer). The vias themselves need to be accurately positioned relative to the first and the second pattern.
In order to position the vias to the first layer and the second layer to the vias, alignment marks are used. A first alignment mark is typically formed by exposing the first layer of photo-resist to an alignment mark pattern followed by some additional steps. Before exposing the third layer of photo-resist, the position of the first alignment mark in the first layer is measured and the third layer is exposed in such a way that vias will be accurately positioned above the first pattern. Likewise, a second alignment mark is formed by exposing the third layer of photo-resist to an alignment mark pattern followed by some additional steps. Before exposing the second layer of photo-resist, the position of the second alignment mark is measured. The second layer is then exposed in such a way that the second pattern will be accurately positioned above the vias.
Known alignment marks (or markers) are gratings including lines and spaces. The position of the alignment gratings is measured by alignment radiation. In order to assure that the alignment radiation does not activate photo-resist, the alignment radiation has a wavelength which differs considerably from the wavelength used in exposure radiation for exposing photo-resist. Roughly, the scale of the lines of the alignment mark is of the order of magnitude of the wavelength of the alignment radiation, and the scale of the smallest features of the circuit patterns is of the scale of the wavelength of the exposure radiation. Because of tolerances in the exposure process used to expose both the circuit patterns as the alignment patterns in one and the same layer of photo-resist, the difference in scale can cause an unwanted shift between the alignment mark and the circuit pattern in a certain photo-resist layer. To prevent this, the lines of the alignment marker are segmented to line segments and space segments so that the features actually exposed when exposing the alignment pattern are of a scale comparable to the scale of the smallest features of the circuit patterns.
Alignment performance depends on the contrast of the alignment markers, which is based on differences in reflectance of alignment radiation between the lines (which are reflecting) and spaces (which are non-reflecting) of the alignment mark.
However, by segmenting the lines of the alignment marker, the contrast of the alignment marker is reduced. This can be understood by visualizing that the area of the reflecting lines is decreased by the area of the non-reflecting space segments.